International Journal of Research in Advanced Electronics Engineering
2025, Vol. 6, Issue 2, Part A
Low-power VLSI architecture for real-time image compression in IoT edge devices
Author(s): John A Thompson and Emily J Carter
Abstract: The growing proliferation of Internet of Things (IoT) applications has created an urgent demand for efficient, real-time image compression directly at the network edge, where power, memory, and computational resources are severely constrained. This study presents the design and implementation of a low-power VLSI architecture for real-time image compression using a hybrid Discrete Wavelet Transform (DWT)-Set Partitioning in Hierarchical Trees (SPIHT) algorithm optimized for IoT edge devices. The proposed architecture integrates advanced low-power design techniques such as clock gating, dynamic voltage and frequency scaling (DVFS), and memory access scheduling, implemented in a 28 nm CMOS process and validated using FPGA prototyping. Benchmarking against state-of-the-art DWT-based compression cores revealed a 36-38% reduction in dynamic power consumption and an average throughput efficiency improvement of 70-100%, while maintaining a Peak Signal-to-Noise Ratio (PSNR) above 32 dB and Structural Similarity Index (SSIM) exceeding 0.91. The system achieved 30 frames per second at 1024×1024 resolution, satisfying real-time constraints for embedded imaging. Experimental analysis confirmed that co-optimization of algorithmic and architectural parameters can significantly reduce energy per frame without compromising compression quality. These results validate the hypothesis that low-complexity, energy-adaptive architectures can effectively balance power, performance, and visual quality in IoT-driven imaging systems. The research offers a scalable foundation for next-generation edge-computing visual processors, enabling sustainable deployment in applications such as smart surveillance, biomedical monitoring, and autonomous sensing. Additionally, the study provides practical recommendations for integrating hybrid compression models, early-stage low-power techniques, and adaptive control logic into future VLSI designs to achieve enhanced energy efficiency in resource-constrained environments.
Pages: 11-16 | Views: 9 | Downloads: 4
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How to cite this article:
John A Thompson, Emily J Carter. Low-power VLSI architecture for real-time image compression in IoT edge devices. Int J Res Adv Electron Eng 2025;6(2):11-16.
