International Journal of Research in Advanced Electronics Engineering
2024, Vol. 5, Issue 1, Part A
Performance analysis of partitioned caches in heterogeneous multi-core CPUs
Author(s): Devi Venkatesh Gowtham and Sweta S Munnoli
Abstract: The quantity of shared cache has been growing with the swift growth of computational speed on the multi-core era. If system architects want to boost system performance, they need to make the most of shared resources. The last-level cache (LLC) is shared by numerous heterogeneous cores in an asymmetric multi-core architecture. The LLC competition is fiercer because heterogeneous cores have different memory access requirements. We present a heterogeneity-aware replacement policy for the partitioned cache (HAPC) that uses cache partitioning to decrease core-to-core interference and uses runtime tracking of the shared reuse state of each cache block within the partition to direct the replacement policy in multithreaded programs to preserve cache blocks shared by multiple cores. When updating the reuse state, the cache replacement policy typically retains cache blocks needed by large cores to improve the efficiency of large cores' LLC accesses, taking into account the difference in memory accesses to LLC and heterogeneous cores. The overall efficiency of the system can be improved by using HAPC to run multithreaded programs, as it significantly improves the performance of big cores while having almost no impact on little cores, in comparison to state-of-the-art cache replacement techniques like LRU and SRCP. Using matrix computing as the working load reduced the L2 cache miss rate by about 12% and increased the IPC by 10% according to the experimental results.
DOI: 10.22271/27084558.2024.v5.i1a.38
Pages: 23-26 | Views: 196 | Downloads: 83
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How to cite this article:
Devi Venkatesh Gowtham, Sweta S Munnoli. Performance analysis of partitioned caches in heterogeneous multi-core CPUs. Int J Res Adv Electron Eng 2024;5(1):23-26. DOI: 10.22271/27084558.2024.v5.i1a.38
