International Journal of Research in Advanced Electronics Engineering
  • Printed Journal
  • Refereed Journal
  • Peer Reviewed Journal

P-ISSN: 2708-4558, E-ISSN: 2708-4566

International Journal of Research in Advanced Electronics Engineering


2022, Vol. 3, Issue 1, Part A
Design and implementation of a combinational lock state system using VHDL


Author(s): US Akor, Peter Makanjuola O, M Hamza and Mustapha M Kabir

Abstract: A combinational lock access control system is a critical link in a security chain. The paper focuses on the implementation of a coded keyless lock. To gain access to the lock, you must first enter a binary code combination. It will unlock the lock if the correct sequence is entered; otherwise, it will remain locked. The ALTERA Design suite was used to create the combination lock state design. The functional verification was carried out using the Quartus II/MaxPlus II package. The Mealy type of Finite State Machine (FSM) is the subject of this report. The output of a sequential circuit is a combination of both the flip-flops' present state and the circuit's input in a Mealy state machine. One of the key hardware description languages utilized in this research to create the Combination Lock system is VHDL (very high-speed integrated circuit HDL). The security technology for machines is discussed in this report. This can be accomplished using the Quartus II/MaxPlus II package. A combination lock state machine is described in this paper as being designed to activate an "unlock" operation when an acceptable binary code is provided, however, the lock can only be opened when the correct code (password) is typed into the system. Because the input data recorded on X during the previous the UNLK result was 0110111 upon 7 clock strikes is 1 when X is 0 (the desired unlock code).

Pages: 01-05 | Views: 30 | Downloads: 16

Download Full Article: Click Here
How to cite this article:
US Akor, Peter Makanjuola O, M Hamza, Mustapha M Kabir. Design and implementation of a combinational lock state system using VHDL. Int J Res Adv Electron Eng 2022;3(1):01-05.
International Journal of Research in Advanced Electronics Engineering